1. Field of the Invention
The present invention relates to an output circuit device, more particularly to an output circuit device which can realize stabilization of the output potential and the power supply potential.
2. Description of the Prior Art
In the recent semiconductor devices, there is a tendency to increase the degree of integration and density in order to reduce the size of the chip, as well as a tendency to increase the driving capability of transistors to make their operation fast.
In order to reduce the chip size, it is necessary to reduce the width of the wiring formed by aluminum or the like . By the reduction in the width of the wiring, the inductive load that exists in the wiring, namely, inductance, will have to be increased. Further, when the current driving capability is increased by increasing the size of the transistor, there will be generated problems that are caused by the increase in the inductive load of the wiring. This problem will now be described by making reference to FIGS. 1 and 2.
FIG. 1 shows an example of the configuration of a general inverter circuit that takes into account the inductance components of the wirings for the power supply and the output. It consists of a P-channel MOS transistor (PMOS transistor) 101 and an N-channel MOS transistor (NMOS transistor) 103. The source terminal of the PMOS transistor 101 is connected to a high level voltage source V.sub.DD that supplies a potential V.sub.DD via an inductance 105 that exists in a power supply wiring made of aluminum, and the source terminal of the NMOS transistor 103 is connected to a low level voltage source V.sub.SS that supplies a potential V.sub.SS (normally OV) via an inductance 107 that exists in a power supply wiring made of aluminum. Further, the PMOS transistor 101 and the NMOS transistor 103 have both of their gate terminals connected to the input terminal IN that inputs a signal to be inverted, and at the same time, their respective drain terminals are connected to the output terminal OUT via an inductance 109 that exists in the output wiring made of aluminum, and the output terminal OUT is connected to a load capacitor 111.
When a low level (potential V.sub.SS) signal is input to the input terminal IN, the PMOS transistor 101 will switch to an on-state and the NMOS transistor 103 will switch to an off-state. Then, a current flows into the load capacitor 111 from the high level voltage source V.sub.DD via the PMOS transistor 101, bringing the output terminal OUT to the high level (potential V.sub.DD). On the contrary, when a high level signal (potential V.sub.DD) is input to the input terminal IN, the PMOS transistor 101 will switch to the off-state and the NMOS transistor 103 to the on-state. Then, charge accumulated in the load capacitor flows into the low level voltage source V.sub.SS via the NMOS transistor 103, bringing the output terminal OUT to a low level (potential V.sub.SS). Therefore, by the operation described above, there will be output from the output terminal OUT a signal which is the inversion of the signal that was input to the input terminal IN.
Now, in an inverter circuit with the above configuration, when the current driving capability of the transistors is enhanced by increasing the transistor size, in order to have a quickly inverted output potential, the on-resistance of the transistors becomes small, and there will be formed, between the high level voltage source V.sub.DD and the load capacitor 111, or between the low level voltage source V.sub.SS and the load capacitor 111, a resonance circuit that consists of the load capacitor and the inductance that exists in the power supply wiring and the output wiring. Then, as shown in FIG. 2, when the input potential changes from potential V.sub.SS to potential V.sub.DD, the NMOS transistor 103 switches to the on-state, and the output potential drops from potential V.sub.DD to potential V.sub.SS. Due to the rapid flow of charge that was accumulated in the load capacitor 111 to the low level voltage source V.sub.SS, a transient current flows in the vicinity of potential V.sub.SS, giving rise to the so-called undershoot phenomenon. On the contrary, when the output potential is raised from potential V.sub.SS to potential V.sub.DD by the rapid charging due to flow of a current to the load capacitor 111 from the high level voltage source V.sub.DD, a transient current flows in the vicinity of potential V.sub.DD, giving rise to the so-called overshoot phenomenon.
As a result, the output potential varies temporarily immediately after it is inverted, giving rise to a problem of transmitting signals at erroneous potentials. Furthermore, it causes variations in the high level voltage source V.sub.DD and the low level voltage source V.sub.SS, which leads to a fear of generating malfunctions in the circuit through variations in the input and output levels of the other elements that are connected to the same power supply wiring.